Field
Embodiments of the present disclosure generally relate to integrated circuit fabrication methods, and in particular, to correcting seam defects in trenches or vias.
Description of the Related Art
Many obstacles exist in the further miniaturization of semiconductor components. One such obstacle is the filling of metal interconnects, which affects the yield of modern CMOS devices. Metal interconnect signal lines make contact to lower conductive layers of the integrated circuit through vias that are formed in an insulating layer. It is desirable to fill the contact and interconnect with the metal that is used to form the interconnect layer so as to insure optimal operation of the device.
Conductive metals, such as copper, are presently the materials of choice for the fabrication of interconnect lines in integrated circuits. Conventional techniques used to fill interconnect lines generally include physical vapor deposition (PVD) or atomic layer deposition (ALD) of a barrier material, followed by a liner and then either copper reflow or electroplating.
When using conventional techniques, problems arise in the interconnect lines from the accumulation of relatively large grains of material at the upper surface of an insulating layer, as well as the accumulation of impurities within the conductive bulk. The accumulation of such grains at the edges of the contact via or interconnect can block or otherwise obstruct the contact or interconnect prior to completely filling the contact or interconnect, resulting in the formation of voids, seems, and uneven structures within the contact or interconnect. The aforementioned problem is particularly acute as integrated circuits are fabricated using smaller geometries.
The smaller contacts that are used in smaller geometry devices, such as contacts or interconnects in the tens of nanometers or less range, necessarily have a larger aspect ratio (i.e., relationship of feature height to width) than do larger geometry devices, thereby exacerbating the contact- or interconnect-filling difficulties described above. For example, unduly large voids can result in line resistance and contact resistance that are appreciably higher than designed. In addition, thinner regions of the conductive material adjacent to the contact or interconnect fill region will be subject to electro migration, which can result in the eventual opening of the circuits and failure of the device.
To address the above issues, other materials and deposition techniques have been considered. When using other fill techniques such as chemical vapor deposition (CVD), cyclical deposition/treat processes are employed. One approach utilizes multiple cycles of deposition and anneal in attempt to repair seams and cavities in the conductive material in low-to-sub atmospheric pressures process regimes. This approach results in extremely slow process time, and attempts to reduce process time have resulted in unsatisfactory resistivity. In other approaches, the deposited metal is subjected to extremely high pressures, such as 700 bar to 2000 bar, or more, in attempt to repair defects in the conductive material. The exerted pressure forces the deposited metal into the undesired voids within the deposited film. However, subsequent thermal post treatment to correct grain boundary defects or other defects results in partial or full reformation of the void. In addition, the pressures utilized in conventional approaches may result in physical damage to low-k dielectric materials adjacent the interconnect.
Therefore, this is a need for an improved method of correcting seam defects.